1. Field of the Invention
This invention relates to computer memory systems and, more particularly, to techniques for reducing power consumption of computer memory systems.
2. Description of the Related Art
Evolving standards for computer memory systems have lead to systems that include greater numbers of higher capacity memory devices. Consequently, computer memory systems have seen an increase in power consumption. One technology in particular, the Fully Buffered Dual Inline Memory Module (FBDIMM), achieves very high memory density by allowing memory modules to be connected in series, rather than in parallel. A parallel architecture suffers from the problem that each additional memory module increases the electrical loading on the parallel data and address buses. The serial point-to-point architecture used by FB-DIMMs overcomes the electrical loading problem since electrical loading is not changed when another module is added. However, the resulting increase in the number of modules that the system can support increases the power consumption of the memory system.
In addition to the above considerations, the demands of the current generation of computers require memory systems to operate at ever increasing clock speeds. The speed of memory modules, rather than the speed of processors, is often the limiting factor for memory transactions. Consequently, computer memory systems have been designed to operate memory modules at the highest possible speeds. Unfortunately, power dissipation is directly proportional to clock speed for a typical memory module. In light of increasing memory densities and clock speeds, what is needed is a mechanism to reduce the power dissipation of individual memory modules within a memory system without significantly reducing access speed or increasing latency.